Wednesday, October 3, 2012

Viva and Written Question For the Post ASIC Design Enginner

Viva and Written Question For the Post ASIC Design Engineer

Q. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q. What is meant by 90nm technology?
Q. What is a transmission gate, and what is its typical use in VLSI?
Q. What is ASIP?
Q. What are the different design styles in VLSI?
Q. What are the differences between gate array ASIC and cell-based ASIC?
Q. When you want the production in the bulk amount which design style you prefer? Justify?
Q. What is EDIF? Explain?
Q. State the importance of Lithography in VLSI design?
Q. Define Baud rate?
Q. What is the relation between DBM and DB?
Q. What do you mean by technology in VLSI design?
Q. What is the technology used in P IV?
Q. What is superscalar architecture?
Q. How do you tackle coupling when design deep submicron SRAM memories?
Q. Power Optimization Techniques for deep sub-micron?
Q. For CMOS logic, give the various techniques you know to minimize power consumption
Q. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Q. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Q. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Q. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Q. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Q. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Q. For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Q. What happens if we increase the number of contacts or via from one metal layer to the next?
Q. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Q. How does Resistance of the metal lines vary with increasing thickness and increasing length?
Q. What are the limitations in increasing the power supply to reduce delay?
Q. What happens to delay if we include a resistance at the output of a CMOS circuit?
Q. What happens to delay if you increase load capacitance?
Q. Give the expression for calculating Delay in CMOS circuit
Q. Give the expression for CMOS switching power dissipation
Q. How do you size NMOS and PMOS transistors to increase the threshold voltage?
Q. Explain sizing of the inverter
Q. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Q. What is ASIC design flow?
Q. What is “Scan” ?
Q. What are RTL, Gate, Metal and FIB fixes? What is a “sewing kits”?
Q. How do you measure the size and density of various programmable logic devices?
Q. What is soft processor? What is hard processor?
Q. What is meant by 90nm technology?
Q. What do you mean by translation and mapping?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is electron migration?
Q. What are the goals of partitioning?
Q. Differentiate Global routing and detailed routing?
Q. What is floor planning? (goals and objectives)
Q. What is the exact difference between floor planning and placement?
Q. Define congestion in routing?
Q. What do you mean by rip-up and re-routing?
Q. What is Yield in fabrication process?
Q. What is the difference between ASIC Design and FPGA Design?
Q. What is floating gate transistor?
Q. Write the characteristics of a cell in a standard cell library?
Q. What is Meta-stability state?
Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.

Viva and Written Question For the Post ASIC Design Enginner

Q. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q. What is meant by 90nm technology?
Q. What is a transmission gate, and what is its typical use in VLSI?
Q. What is ASIP?
Q. What are the different design styles in VLSI?
Q. What are the differences between gate array ASIC and cell-based ASIC?
Q. When you want the production in the bulk amount which design style you prefer? Justify?
Q. What is EDIF? Explain?
Q. State the importance of Lithography in VLSI design?
Q. Define Baud rate?
Q. What is the relation between DBM and DB?
Q. What do you mean by technology in VLSI design?
Q. What is the technology used in P IV?
Q. What is superscalar architecture?
Q. How do you tackle coupling when design deep submicron SRAM memories?
Q. Power Optimization Techniques for deep sub-micron?
Q. For CMOS logic, give the various techniques you know to minimize power consumption
Q. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Q. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Q. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Q. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Q. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Q. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Q. For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Q. What happens if we increase the number of contacts or via from one metal layer to the next?
Q. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Q. How does Resistance of the metal lines vary with increasing thickness and increasing length?
Q. What are the limitations in increasing the power supply to reduce delay?
Q. What happens to delay if we include a resistance at the output of a CMOS circuit?
Q. What happens to delay if you increase load capacitance?
Q. Give the expression for calculating Delay in CMOS circuit
Q. Give the expression for CMOS switching power dissipation
Q. How do you size NMOS and PMOS transistors to increase the threshold voltage?
Q. Explain sizing of the inverter
Q. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Q. What is ASIC design flow?
Q. What is “Scan” ?
Q. What are RTL, Gate, Metal and FIB fixes? What is a “sewing kits”?
Q. How do you measure the size and density of various programmable logic devices?
Q. What is soft processor? What is hard processor?
Q. What is meant by 90nm technology?
Q. What do you mean by translation and mapping?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is electron migration?
Q. What are the goals of partitioning?
Q. Differentiate Global routing and detailed routing?
Q. What is floor planning? (goals and objectives)
Q. What is the exact difference between floor planning and placement?
Q. Define congestion in routing?
Q. What do you mean by rip-up and re-routing?
Q. What is Yield in fabrication process?
Q. What is the difference between ASIC Design and FPGA Design?
Q. What is floating gate transistor?
Q. Write the characteristics of a cell in a standard cell library?
Q. What is Meta-stability state?
Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.

Viva and Written Question For the Post ASIC Design Enginner

Q. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q. What is meant by 90nm technology?
Q. What is a transmission gate, and what is its typical use in VLSI?
Q. What is ASIP?
Q. What are the different design styles in VLSI?
Q. What are the differences between gate array ASIC and cell-based ASIC?
Q. When you want the production in the bulk amount which design style you prefer? Justify?
Q. What is EDIF? Explain?
Q. State the importance of Lithography in VLSI design?
Q. Define Baud rate?
Q. What is the relation between DBM and DB?
Q. What do you mean by technology in VLSI design?
Q. What is the technology used in P IV?
Q. What is superscalar architecture?
Q. How do you tackle coupling when design deep submicron SRAM memories?
Q. Power Optimization Techniques for deep sub-micron?
Q. For CMOS logic, give the various techniques you know to minimize power consumption
Q. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Q. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Q. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Q. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Q. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Q. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Q. For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Q. What happens if we increase the number of contacts or via from one metal layer to the next?
Q. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Q. How does Resistance of the metal lines vary with increasing thickness and increasing length?
Q. What are the limitations in increasing the power supply to reduce delay?
Q. What happens to delay if we include a resistance at the output of a CMOS circuit?
Q. What happens to delay if you increase load capacitance?
Q. Give the expression for calculating Delay in CMOS circuit
Q. Give the expression for CMOS switching power dissipation
Q. How do you size NMOS and PMOS transistors to increase the threshold voltage?
Q. Explain sizing of the inverter
Q. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Q. What is ASIC design flow?
Q. What is “Scan” ?
Q. What are RTL, Gate, Metal and FIB fixes? What is a “sewing kits”?
Q. How do you measure the size and density of various programmable logic devices?
Q. What is soft processor? What is hard processor?
Q. What is meant by 90nm technology?
Q. What do you mean by translation and mapping?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is electron migration?
Q. What are the goals of partitioning?
Q. Differentiate Global routing and detailed routing?
Q. What is floor planning? (goals and objectives)
Q. What is the exact difference between floor planning and placement?
Q. Define congestion in routing?
Q. What do you mean by rip-up and re-routing?
Q. What is Yield in fabrication process?
Q. What is the difference between ASIC Design and FPGA Design?
Q. What is floating gate transistor?
Q. Write the characteristics of a cell in a standard cell library?
Q. What is Meta-stability state?
Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.

Viva and Written Question For the Post ASIC Design Enginner

Q. What is meant by scaling in VLSI design? Describe various effects of scaling.
Q. What is meant by 90nm technology?
Q. What is a transmission gate, and what is its typical use in VLSI?
Q. What is ASIP?
Q. What are the different design styles in VLSI?
Q. What are the differences between gate array ASIC and cell-based ASIC?
Q. When you want the production in the bulk amount which design style you prefer? Justify?
Q. What is EDIF? Explain?
Q. State the importance of Lithography in VLSI design?
Q. Define Baud rate?
Q. What is the relation between DBM and DB?
Q. What do you mean by technology in VLSI design?
Q. What is the technology used in P IV?
Q. What is superscalar architecture?
Q. How do you tackle coupling when design deep submicron SRAM memories?
Q. Power Optimization Techniques for deep sub-micron?
Q. For CMOS logic, give the various techniques you know to minimize power consumption
Q. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
Q. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
Q. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
Q. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
Q. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
Q. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Q. For an NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
Q. What happens if we increase the number of contacts or via from one metal layer to the next?
Q. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
Q. How does Resistance of the metal lines vary with increasing thickness and increasing length?
Q. What are the limitations in increasing the power supply to reduce delay?
Q. What happens to delay if we include a resistance at the output of a CMOS circuit?
Q. What happens to delay if you increase load capacitance?
Q. Give the expression for calculating Delay in CMOS circuit
Q. Give the expression for CMOS switching power dissipation
Q. How do you size NMOS and PMOS transistors to increase the threshold voltage?
Q. Explain sizing of the inverter
Q. What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
Q. What is ASIC design flow?
Q. What is “Scan” ?
Q. What are RTL, Gate, Metal and FIB fixes? What is a “sewing kits”?
Q. How do you measure the size and density of various programmable logic devices?
Q. What is soft processor? What is hard processor?
Q. What is meant by 90nm technology?
Q. What do you mean by translation and mapping?
Q. What is Back annotation?
Q. What is DRC and LVS and name some tools which are used for these operations?
Q. What is electron migration?
Q. What are the goals of partitioning?
Q. Differentiate Global routing and detailed routing?
Q. What is floor planning? (goals and objectives)
Q. What is the exact difference between floor planning and placement?
Q. Define congestion in routing?
Q. What do you mean by rip-up and re-routing?
Q. What is Yield in fabrication process?
Q. What is the difference between ASIC Design and FPGA Design?
Q. What is floating gate transistor?
Q. Write the characteristics of a cell in a standard cell library?
Q. What is Meta-stability state?
Q. Setup time and hold time in digital circuits.
Q. False path in FPGA’s, Critical path, Negative slack, Jitter vs. clock skew .
Q. Routing delay, Flop to out delay, Flop to flop delay, Pad to flop delay, Board delay.
Q. Knowledge of Synthesis and layout constraints.

Monday, October 1, 2012

Question for the position ASIC Design Engineer

Do you have any experience in platform ASIC design?
Why did you choose a career in ASIC?
What methods do you use to add to your training of ASIC design?
What areas of ASIC design and engineering do you feel you could improve upon?
How do you continue your education in design circuitry?
What attracted you to our company?
Tell me about your training, internship, graduate school, etc, and why that makes you an excellent engineer prospect for us.
Have you been involved in a full custom design before? Tell me about it.
What do you know about the history of ASIC?
What design tools do you use?
Explain to me what an application specific integrated circuit is or would be?
What was your most complex circuit design at your current or previous employment?
What areas of ASIC design do you feel the most challenging?
Walk me through your planning steps for designing a new ASIC.

Click Here for More Question for ASIC Design Engineer.


To learn about Oracle.    To learn about Oracle. 

Thursday, September 27, 2012

Update Product Information

Thursday, September 20, 2012

Network Hardware and System Maintenance for ABC Bank Limited

Here I give 50 question on Network, Hardware and System Maintenance of any online Bank in the world. An IT executive of any Bank in the world can easily judge branch level User and Support Team. You can rectification the bellow question for your organization. I think this will help you.

For Ans. stay close with  this blog.

Question: Network Hardware and System Maintenance for  any online Bank in the world. Here ABC-CBS is a core banking solution for  any online Bank in the world.
        
1.Which one is a valid IP address?   
a. 172.16.1.10
b. 172.16.256.10
c. 300.168.1.10  
     
2.Select any two accessories/parts needed to establish a LAN   
a. LAN card
b. SWITCH
c. Flopy Disk         

3.Your IP is 192.168.1.5 and Server IP is 192.168.1.253. How you will test the physical connectivity?
a. ping 192.168.1.253
b. test 192.168.1.253
c. vpn 192.168.1.253
     
4.If you see cross mark in the local area connection icon, what will you do?   
a. Check the cable connectivity
b. Restart the Router
c. Check the media converter   
  
5.What will you do if you see any led (light) of media converter is off ?    
a. Inform to IT Division
b. Inform to ID Division
c. Do nothing  
    
6.How do you understand the router's power is on ?   
a. Check the router's led.
b. Check the switch led.
c. disconnecting the cable.   
    
7.What is the definition of WAN?   
a. Two Computer's Connected Within a building
b. Two Computer's connected within a university campus.
c. two computer's connected where geographical area is undefined.  
    
8.What is the definition of MAN?   
a. Two Computer's Connected Within a building.
b. Two Computer's connected within a city.
c. two computer's connected where geographical area is undefined.  
    
9.What is the definition of LAN?   
a. Two Computer's Connected Within a building.
b. Two Computer's connected within a city.
c. two computer's connected where geographical area is undefined.   
     
10.How you understand that the switch port is not working correctly?   
a. port indicator light is showing Green
b. port indicator light is showing Orange
c. port indicator light is showing Red  
    
11.What is the connectivity flow for online branches?   
a. Media Converter ->Router ->Switch ->Server/Computer
b. Router ->Switch ->Media Converter ->Server/Computer
c. Media Converter ->Server/Computer ->Router  
    
12. Which command show's the IP Address details from the DOS mode/Command Prompt?   
a. ipconfig
b. configure
c. showip  
     
13.One IP address can be assigned in two or more computer's in a branch ?   
a. True
b. False   
     
14.All computer's of a branch are connected through?   
a. Router
b. Media Converter
c. Switch   
    
15.Which Device provides network security in your branch?   
a. Router
b. Media Converter
c. Switch  
    
16.Which device is directly connected with fiber optic cable in your branch?   
a. Router
b. Media Converter
c. Switch   
     
17.Which device converts light signal to electrical signal?   
a. Router
b. Media Converter
c. Switch  
    
18.Which device is provided by ISP, a link provider for our Bank?   
a. Router
b. Media Converter
c. MUX  
     
19.Which cable performance is better?   
a. CAT-5
b. CAT-6
c. CAT-2   
     
20.Which DOS command is used to check the computer connectivity?   
a. ipconfig
b. ping
c. test 
     
21.Which communication media is not used to connect from branch to head office?   
a. Fiber Optic Cable
b. VSAT
c. Radio     
 
22.Which one is not an advantage of networking?   
a. Store Data
b. Sharing Information
c. Centralized Administration  
    
23.Branch users can login to ABC-CBS although the branch server is out of network.   
a. True
b. False   
   
24.What type of server is used in an online branch?   
a. Application Server
b. Oracle Database Server
c. None of the above 
       
25.What type of server is used in an offline branch?   
a. Application Server
b. Oracle Database Server
c. None of the above   
    
26.ABC Bank has centralized online banking network.   
a. True
b. False
      
27.Why do we share the ABC-CBS folder?   
a. For network printing
b. For VPN Connection
c. To access ABC-CBS
     
28.Why Antivirus software is used?   
a. To clean viruses
b. To delete ABC-CBS user
c. To create new folder  
     
29.Which Antivirus softwares are used in our Bank ?   
a. Kaspersky &Escan
b. Norton
c. Juniper  
     
30.The antivirus software should update regularly.   
a. True
b. False  
     
31.What is an Operating System?   
a. A software
b. A hardware
c. A firmware   
   
32.Which one is a popular Operating System?   
a. Windows XP
b. Adobe Acrobat Reader
c. Windows Real Player   
     
33.Why do we enable remote desktop?   
a. For remote management
b. For better performance
c. For antivirus activities 
    
34.Why do we use hard drives?  
a. For playing music
b. For storing data
c. For printing documents 
    
35.Generally in which drive we install our operating system?   
a. In D Drive
b. In C Drive
c. In E Drive  
    
36.We can protect our folder with password without using any third-party software.   
a. True
b False   
    
37.Why do we create folder?   
a. To Organize Data
b. To install software
c. To format data   
   
38.Which one is the correct  VPN server IP address?    
a. 203.76.98.254
b. 203.76.98.212
c. 203.76.98.155 
    
39.Which is the pre-condition to establish the VPN connectivity?   
a. Modem must be installed in the existing  PC running with ABC-CBS having internet connection.
b. Must be connect the modem with internet.
c. Uninstall the previous VPN connection.   
      
40.The operating system manages    
a. Memory
b. Process
c. all of the above 
    
41.Which is not the function of the Operating System?   
a. Memory Management
b. Disk Management
c. Documents Printing  
    
42.In which purpose we configure VPN connection?   
a. To check the online connectivity only
b. For internet use only
c. To connect Head Office database server for ABC-CBS       
                 
43.What will be required to authenticate VPN server?   
a. User ID and Password
b. User ID Only
c. Password Only   
    
44.VPN stands for-   
a. Virtual Peer Network
b. Virtual Private Network
c. Very People Network  
     
45.What is the maximum validation period of a ABC-CBS user password?   
a. 3 months
b. 1 month
c. 10 days
    
46.What is the minimum character length of a ABC-CBS user password?   
a. 100 character
b. 9 character
c. 15 character 
    
47.Which software is used for Forms and Reports?   
a. Developer 6i
b. Developer 2000
c. Developer 10g   
    
48.Why TNSNAMES.ORA is used?   
a. To Connect Server
b. To Connect Database
c. To Connect Workstation. 
     
49.ABC-CBS shortcut uses IP address of-   
a. Head Office Server
b. Branch Office Server
c. DNS Server  
     
50.When TNSNAMES.ORA is created?   
a. When Developer 6i is installed
b. When Oracle database is installed
c. When Operating System is installed  
                                                                       

Wednesday, September 19, 2012

Question sheet of Online Transaction System - 2012


1.    Which is applicable for online transaction in individual batch ?
        a)    Only one set of transaction is possible
        b)    More than one set of transaction  are possible
        c)    Only checking A/Cs transaction are possible
2.    After release the cash transaction at online transaction we can do?
        a)    Only delete
        b)    Only reverse
        c)    Both of the above are allowed
3.    What happen at originating branch at the time of remote transfer?
        a)    No transaction at originating branch
        b)    One transaction at originating branch
        c)    Two transaction at originating branch
4.    Which is the first step at the time of remote transfer transaction?
        a)    First credit then debit
        b)    First debit then credit
        c)    Both of the above are allowed
5.    Which is the IBTA transaction code for online transaction?
        a)    35
        b)    40
        c)    51
6.    When the debit & credit amount of IBTA checklist with the amount of PBG in clean cash are mismatch?
        a)    When online transactions are deleted
        b)    When online transactions are reversed
        c)    Both of the above
7.    Which is require for an online transaction delete or reverse?
        a)    Only batch
        b)    Only serial
        c)    Batch & serial both
8.    When a transaction are reverse then ?
        a)    Will not show in transaction checklist reports
        b)    Will not show in A/C statement reports
        c)    Both of the above
9.    What happen at agent commission when CLS installments are posting by online?
         a)    Auto posting without (60-40)% of  agent commission
         b)    Auto posting is not possible
         c)    Auto posting including (60-40)% of  agent commission
10.    What is the effect of A/C restriction at online transaction?
        a)    To increase debit amount
        b)    To decrease debit amount
        c)    To fixed one or more branch for online transaction
11.    Who will perform auto clearing process at online clearing transaction?
a)    Originating branch
b)    Responding branch
c)    Anyone can process
12.    What happen at PBG in Local branch at the time of  “Deposit by cash” transaction?
a)    PBG Debit
b)    PBG credit
c)    Only cash credit

13.    What is the transaction status at the time of Remote transfer on online transaction?
a)    ‘P’
b)    ‘N’
c)    ‘R’
14.    What happen when batch 52 is reverse with batch 82 at online transaction?
a)    Status of batch 52 is ‘N’ & Status of batch 52 is ‘R’
b)    Status of batch 52 is ‘R’ & Status of batch 52 is ‘N’
c)    Status of both batch is ‘N’
d)    Status of both batch is ‘R’
15.    What to do when wrongly posted online Clearing transaction?
a)    Have to Delete
b)    Have to Reverse
c)    Have to Clearing Return
16.    What is the transaction code at Clearing Return transaction?
a)    10
b)    11
c)    22
17.    In online transaction what is the process to balance transfer at two different A/C of same branch?
a)    Transfer Deposit
b)    Remote Transfer
c)    Transfer By Cheque
18.    If an online branch is close at Saturday then what happen?
a)    Transaction is allowed from other online branch
b)    Transaction is not allowed from other online branch
c)    Have to inform the responding branch to do the transaction
19.    How many transactions are happen at Remote Transfer Transaction of two chequing A/C?
        a)    3
        b)    4
        c)    6
20.    How many transactions are happen when CLS Installment are deposit by cash at online transaction?
       a)    9
       b)    10
       c)    12

These are the user testing questions of a Banking Software.
 
For Answer the above Question please send me an email.
email: sksarker.ru@gmail.com

Thakns.

Thursday, September 13, 2012

XHTML and HTML Syllabus for odesk test. It's free.

You can earn money from home. Just signup in odesk. It is free. You have to complete your profile and take some test. It is also free. Here are some exam test syllabus. See the HTML syllabus which are given bellow. 

 
i) XHTML 1.0 Test:

-Fundamentals
-Tags
-Images and Links
-Tables and Forms


ii) HTML 4.01:

-Advanced Tags
-Fundamentals
-Tags
-Tables
-Links and Images
-Forms and Frames


iii) HTML 5 Test:

-HTML 5 Elements and attributes
-HTML 5 Events
-HTML 5 syntax
-HTML 5 Web application APIs
-Loading HTML 5 Web pages

Wednesday, September 12, 2012

Introducing a new YouTube app for your iPhone and iPod touch


New YouTube app for your iPhone and iPod touch

For all you reactionary YouTube fans out there who cannot get as much as necessary YouTube on your mobile, we have got some huge news: starting yesterday, you can download the official YouTube app for iPhone and iPod touch from the App Store, bringing you more of the videos you love and more ways to share them with the people you think about.

The recent app is built by YouTube engineers, to give our iPhone and iPod touch users the best mobile experience. Here’s what you’ll find:

Thousands (10,000) of more videos: Watch official melody videos like Taylor’s latest hit.

Latest YouTube channel guide: Swipe your finger from the left edge of the screen to reveal a guide with your subscribed channels on YouTube, giving you instant access to everything from Alli Sports to YOMYOMF.

Find amazing videos faster: Obtain to videos like “Gangnam Style” faster with new search tools that give suggestions while you type, and let you sort through videos or channels. Flip through related videos, comments and more info, all while watching a video.


More ways to separate with the people you care for: Share that incredible video you found on YouTube on Google+, Face book or text message in the app, as well as from Twitter and email.

There is even extra to explore with the new YouTube app for iPhone and iPod touch, available for download from the App Store today. We’re working on an optimized version of the YouTube app for iPad in the coming months, and stay tuned for more details.



You have already exposed us you love YouTube on mobile—to the tune of 1 billion mobile views a day—so we cannot wait to see what you believe about this new experience.